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SLG7NT41563 fog project SLG7NT41563_ds_r012 rev 0.12 revised december 22, 2016 SLG7NT41563_gp_r002 silego technology, inc. preliminary for internal use only this datasheet is for internal use only ? do not distribute ou tside of silego and intel.
silego technology, inc. preliminary SLG7NT41563 fog project SLG7NT41563_ds_r012 SLG7NT41563_gp_r002 rev 0.12 revised december 22, 2016 general description features ? low power consumption ? pb - free / rohs compliant ? halogen - free ? s t qfn - 20 package output summary ? 2 outputs ? push pull 1x ? 2 outputs ? push pull 2x ? 4 outputs ? open drain nmos 2x pin configuration 1 2 3 4 5 6 7 11 8 9 10 20 19 18 s t q fn - 20 top view 12 13 14 15 16 17 vdd SLG7NT41563 gnd pch_pwrok slp_s3_n vddq_pwrgd v12s_pwrgd v3p3s_pwrgd tpm_rsmrst_pwrgd vcc_1p0a_pwrgd vr_ready all_sys_pwrgd pch_syspwrok pwrgd_ps all_sys_pwrgd_n all_sys_pwrgd_no_gate vccio_enable latched_bkf_cut backfeed_cut_dsw_n nc rsmrst_pwrgd silego SLG7NT41563 is a low power and small form device. the soc is housed in a 2mm x 3mm stqfn package which is optimal for using with small devices.
preliminary page 3 3 fog project SLG7NT41563_ds_r012 SLG7NT41563 block diagram
preliminary page 4 4 fog project SLG7NT41563_ds_r012 SLG7NT41563 p in configuration pin # pin name type pin description 1 vdd pwr supply voltage 2 pch_pwrok digital input digital input without schmitt trigger 3 slp_s3_n digital input digital input without schmitt trigger 4 vddq_pwrgd digital input digital input without schmitt trigger 5 v12s_pwrgd digital input digital input without schmitt trigger 6 v3p3s_pwrgd digital input digital input without schmitt trigger 7 tpm_rsmrst_pwrgd digital input digital input without schmitt trigger 8 vcc_1p0a_pwrgd digital input digital input without schmitt trigger 9 vr_ready digital input digital input with schmitt trigger 10 all_sys_pwrgd digital output push pull 2x 11 gnd gnd ground 12 pch_syspwrok digital output open drain nmos 2x 13 pwrgd_ps digital input digital input without schmitt trigger 14 all_sys_pwrgd_n digital output push pull 1x 15 all_sys_pwrgd_no_ga te digital output push pull 1x 16 nc -- keep floating or connect to gnd 17 rsmrst_pwrgd digital output push pull 2x 18 vccio_enable digital output open drain nmos 2x 19 latched_bkf_cut digital output open drain nmos 2x 20 backfeed_cut_dsw_n digital output open drain nmos 2x ordering information part number package type SLG7NT41563v v= s tqfn - 20 SLG7NT41563vtr vtr= s tqfn - 20 ? tape and reel (3k units)
preliminary page 5 5 fog project SLG7NT41563_ds_r012 SLG7NT41563 absolute maximum conditions parameter min. max. unit v high to gnd - 0.3 7 v voltage at input pins - 0.3 7 v current at input pin - 1.0 1.0 ma storage temperature range - 65 125 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 13 00 -- v moisture sensitivity level 1 electrical characteristics (@ 25c, unless otherwise stated) symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 3.3 5.5 v t a operating temperature - 40 25 85 c i q quiescent current static inputs and outputs -- 1 -- a v o maximal voltage applied to any pin in high - impedance state -- -- vdd v i o maximal average or dc current (note 1) per each chip side (pin2 - pin10, pin12 - pin20) -- -- 90 ma v ih high - level input voltage logic input, at vdd=1.8v 1.10 -- vdd v logic input with schmitt trigger, at vdd=1.8v 1.27 -- vdd logic input, at vdd=3.3v 1.78 -- vdd logic input with schmitt trigger, at vdd=3.3v 2.13 -- vdd logic input, at vdd=5.0v 2.64 -- vdd logic input with schmitt trigger, at vdd=5.0v 3.16 -- vdd v il low - level input voltage logic input, at vdd=1.8v -- -- 0.69 v logic input with schmitt trigger, at vdd=1.8v -- -- 0.44 logic input, at vdd=3.3v -- -- 1.21 logic input with schmitt trigger, at vdd=3.3v -- -- 0.95 logic input, at vdd=5.0v -- -- 1.84 logic input with schmitt trigger, at vdd=5.0v -- -- 1.51 i ih high - level input current logic input pins; v in = vdd - 1.0 -- 1.0 a i il low - level input current logic input pins; v in = 0v - 1.0 -- 1.0 a v oh high - level output voltage push pull & pmos od, i oh = 100ua, 1x driver, at vdd=1.8 v 1.69 1.789 -- v
preliminary page 6 6 fog project SLG7NT41563_ds_r012 SLG7NT41563 push pull & pmos od, i oh = 100ua, 2x driver, at vdd=1.8 v 1.7 1.794 -- push pull & pmos od, i oh = 3ma, 1x driver, at vdd=3.3 v 2.735 3.12 -- push pull & pmos od, i oh = 3ma, 2x driver, at vdd=3.3 v 2.87 3.21 -- push pull & pmos od, i oh = 5ma, 1x driver, at vdd=5.0 v 4.19 4.78 -- push pull & pmos od, i oh = 5ma, 2x driver, at vdd=5.0 v 4.32 4.89 -- v ol low - level output voltage push pull, i ol = 100ua, 1x driver, at vdd=1.8 v -- 0.008 0.03 v push pull, i ol = 100ua, 2x driver, at vdd=1.8 v -- 0.004 0.01 open drain, i ol = 100ua, 2x driver, at vdd=1.8 v -- 0.003 0.01 push pull, i ol = 3ma, 1x driver, at vdd=3.3 v -- 0.13 0.228 push pull, i ol = 3ma, 2x driver, at vdd=3.3 v -- 0.060 0.108 open drain, i ol = 3ma, 2x driver, at vdd=3.3 v -- 0.04 0.08 push pull, i ol = 5ma, 1x driver, at vdd=5.0 v -- 0.157 0.270 push pull, i ol = 5ma, 2x driver, at vdd=5.0 v -- 0.076 0.140 open drain, i ol = 5ma, 2x driver, at vdd=5.0 v -- 0.051 0.11 i oh high - level output current push pull & pmos od, v oh = v dd - 0.2, 1x driver, at vdd=1.8 v 1.066 1.703 -- ma push pull & pmos od, v oh = v dd - 0.2, 2x driver, at vdd=1.8 v 2.216 3.406 -- push pull & pmos od, v oh = 2.4 v, 1x driver, at vdd=3.3 v 6.045 12.08 -- push pull & pmos od, v oh = 2.4 v, 2x driver, at vdd=3.3 v 11.522 24.16 -- push pull & pmos od, v oh = 2.4 v, 1x driver, at vdd=5.0 v 22.08 34.04 -- push pull & pmos od, v oh = 2.4 v, 2x driver, at vdd=5.0 v 41.69 68.08 -- i ol low - level output current push pull, v ol =0.15v, 1x driver, at vdd=1.8 v 0.917 1.689 -- ma push pull, v ol =0.15v, 2x driver, at vdd=1.8 v 1.834 3.378 -- open drain, v ol =0.15v, 2x driver, at vdd=1.8 v 2.750 5.068 -- push pull, v ol =0.4v, 1x driver, at vdd=3.3 v 4.875 8.244 -- push pull, v ol =0.4v, 2x driver, at vdd=3.3 v 9.750 16.488 -- open drain, v ol =0.4v, 2x driver, at vdd=3.3 v 14.541 24.74 --
preliminary page 7 7 fog project SLG7NT41563_ds_r012 SLG7NT41563 push pull, v ol =0.4v, 1x driver, at vdd=5.0 v 7.215 11.58 -- push pull, v ol =0.4v, 2x driver, at vdd=5.0 v 13.831 23.16 -- open drain, v ol =0.4v, 2x driver, at vdd=5.0 v 17.343 34.76 -- r pull_down internal pull down resistance pull down on pin 13 700 1000 1300 k ? t dly0 delay0 time at temperature 25c 9.09 10.1 10.6 ms at temperature - 40c +85c (note 1) 8.24 10.1 12.55 t su start up time from vdd rising past 1.35v -- 0.3 -- ms 1. guaranteed by design.
preliminary page 8 8 fog project SLG7NT41563_ds_r012 SLG7NT41563 functionality waveforms d0 ? pin#2 ( pch_pwrok ) d1 ? pin#3 ( slp_s3_n ) d2 ? pin#4 ( vddq_pwrgd ) d3 ? pin#13 ( pwrgd_ps ) d4 ? pin#5 ( v12s_pwrgd ) d5 ? pin#6 ( v3p3s_pwrgd ) d6 ? pin#7 ( tpm_rsmrst_pwrgd ) d7 ? pin#8 ( vcc_1p0a_pwrgd ) d8 ? pin#20 ( backfeed_cut_dsw_n ) with external 5k ? pull up resistor d9 ? pin#19 ( latched_bkf_cut ) with external 5k ? pull up resistor d10 ? pin#12 ( pch_syspwrok ) with external 5k ? pull up resistor d11 ? pin#18 ( vccio_enable ) with external 5k ? pull up resistor d12 ? pin#17 ( rsmrst_pwrgd ) 1. device functionality
preliminary page 9 9 fog project SLG7NT41563_ds_r012 SLG7NT41563 d0 ? pin#3 ( slp_s3_n ) d1 ? pin#9 ( vr_ready ) d2 ? pin#15 ( all_sys_pwrgd_no_gate ) d3 ? pin#14 ( all_sys_ pwrgd_n ) d4 ? pin#10 ( all_sys_pwrgd ) 2. device functionality
preliminary page 10 10 fog project SLG7NT41563_ds_r012 SLG7NT41563 package top marking datasheet revision programming code number locked status part code revision date 0.12 002 l 41563 aa 12/22/2016 the ic security bit is locked/set for code security for production unless otherwise specified. revis ion number is not changed for bit locking .
preliminary page 11 11 fog project SLG7NT41563_ds_r012 SLG7NT41563 package drawing and dimensions 20 lead s t q fn package jedec mo - 220, variation wece ic net weight: 0.0086 g
preliminary page 12 12 fog project SLG7NT41563_ds_r012 SLG7NT41563 tape and reel specification package type # of pins nominal package size (mm) max units reel & hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch s t q fn 20l 2 x3 mm 0.4p green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 carrier tape drawing and dimensions package type pocket btm length (mm) pocket btm width (mm) pocket depth (mm) index hole pitch (mm) pocket pitch (mm) index hole diameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) tape width (mm) a0 b0 k0 p0 p1 d0 e f w s t q fn 20l 2 x3 mm 0.4p green 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 refer to eia - 481 specifications recommended reflow soldering profile please see ipc/jedec j - std - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). more information can be found at www.jedec.org .
preliminary page 13 13 fog project SLG7NT41563_ds_r012 SLG7NT41563 datasheet revision history date version change 12 / 14 /201 6 0.10 new design for slg46 722 chip 12/15/2016 0.11 added pin15, corrected dly0 time and pin14 name 12/22/2016 0.12 updated device revision summary
preliminary page 14 14 fog project SLG7NT41563_ds_r012 SLG7NT41563 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding silego green products, please visit our website . our green product lines feature: greenpak1 / greenpak2 / greenpak3/ greenpak 4 / greenpak 5: programmable mixed signal matrix product s greenfet1 / greenfet3: mosfet drivers and ultra - small, low rdson load switches greenclk1 / greenclk2 / greenclk3: crystal replacement technology products are also available for purchase directly from silego at the silego online store at http://www.silego.com/buy/ . silego technical support datasheets and errata, application notes and example designs, user guides, and hardware support docu ments and the latest software releases are available at the silego website or can be requested directly at info@silego.com. for specific greenpak design or applications questions and support please send e - mail requests to greenpak@silego.com users of silego products can receive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for suppo rt. local sales offices a re also available to help customers. more information regarding your local representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted directly via e - mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminars and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. silego technology does not assume any liability arising out of such applications or uses of its products. silego technology reserves the right to improve product design, functions and reliability without notic e

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